Today's demand for ever-increasing bandwidth continues to push the limits of broadband packet network processors. Such processors interconnect optical fiber segments that make up the backbone of packet networks (such as the Internet) and are employed to switch data among the segments to route them rapidly through the network. As the data traverse the processors, they must be tracked and made to conform to various protocols. Accordingly, the processors themselves include hardware for tracking the data and translating them among the various protocols. This hardware includes serializer/deserializer crossconverters, forward error correctors, framers, mappers, traffic classification and management co-processors, network processors, control plane processors and backplane physical layer interfaces, and switch fabrics.
In practice, this hardware is implemented in application-specific integrated circuits (ASICs), application-specific standard product integrated circuits (ASSPs) or other integrated circuits (ICs). These ASICs, ASSPs and ICs must be coupled to one another to form the processor.
Unfortunately, coupling these circuits together has proven problematic. Interface mismatches occur when the signals that the circuits transmit or expect to receive are not identical. Interface mismatches also occur when transmit and receive speeds differ.
The conventional approach to addressing this problem has been to place a “bridge” between the circuits that are to be coupled to one another. Often, bridges are made from field-programmable gate arrays (FPGAs). Logic within the FPGA modifies or buffers data as necessary to provide the proper interface. Though they are flexible, FPGAs are expensive. Today's data rates are also becoming too great for FPGAs to handle.
ASICs can be used instead of FPGAs. The logic within the FPGAs can be effected within an ASIC, but time and money are required. Further hampering the adoption of ASICs is the fact that they are not readily modifiable should interface requirements change.
Accordingly, what is needed in the art is a new architecture that has at least some of the speed, size and cost advantages of ASICs, but the flexibility of FPGAs.